System Architecture Directions for Post-SoC/32-bit Networked Sensors

Hyung-Sin Kim Networks, Systems

The emergence of low-power 32-bit Systems-on-Chip (SoCs), which integrate a 32-bit MCU, radio, and flash, presents an opportunity to re-examine design points and trade-offs at all levels of the system architecture of networked sensors. To this end, we develop a post-SoC/32-bit design point called Hamilton, showing that using integrated components enables a ∼$7 core and shifts hardware modularity to design time. We study the interaction between hardware and embedded OSes, identifying that (1) post-SoC motes provide lower idle current (5.9 µA) than traditional 16-bit motes, (2) 32-bit MCUs are a major energy consumer (e.g., tick increases idle current >50 times), comparable to radios, and (3) thread-based concurrency is viable, requiring only 8.3 µs of context switch time. We design a system architecture, based on a tickless multithreading OS, with cooperative/adaptive clocking, advanced sensor abstraction, and preemptive packet processing. Its efficient MCU control improves concurrency with ∼30% less energy consumption. Together, these developments set the system architecture for networked sensors in a new direction.

Published On: November 4, 2018

Presented At/In: The 16th ACM Conference on Embedded Networked Sensor Systems (SenSys ’18)

Download Paper: http://bets.cs.berkeley.edu/publications/2018sensys_hamilton.pdf

Authors: Hyung-Sin Kim, Michael Andersen, Kaifei Chen, Sam Kumar, William J. Zhao, Kevin Ma, David Culler